Electronic Design

A Methodology to Speed DFT Signoff

Shipping high-quality ICs requires that design-for-test (DFT) methodologies be included in a design. DFT provides external access at the device’s I/O pins to internal registers to either control or ...
Electronic Design

Design-For-Test The Smart Way: dFT With A "Big T" And A "Little d"

Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding ...
EDN

ITC tutorials span DFT basics to RF test

The 2006 International Test Conference is scheduled for the week of October 22 in Santa Clara, CA. For more on this year’s ITC, read our interview with program chair Anne Gattiker. Semiconductor test ...
Semiconductor Engineering

Making IC Test Faster And More Accessible: Part 1

The fundamental challenges of IC test have been the same for a long time. At the heart of all test strategies is controllability and observability. First, control the state of the chip with known test ...
EDN

DFT software tackles test costs

BALTIMORE — The marriage of design-for-test (DFT) software with test hardware may drastically lower the cost of test, according to several companies that will present their plans at this week's ...